职位描述

Job
Description:
DFT related task, such as ATPG,
MBIST, Boundary Scan etc
·
Responsible for whole chip or sub system level DFT
architecture definition and DFT planning for complex SoC design;
·
Perform design implementation and verification on test
modules, scan insertion, test compression, Memory Build In Self Test,
JTAG/Boundary scan.
·
Be responsible to improve the testability of IP and chip to
meet test coverage requirement.
Qualifications:
·
Master Degree, Major in Electrical Engineering or related
disciplines master
·
Good English skills, both oral and written
·
Basic knowledge about ATPG/SCAN/Memory BIST
·
Scripting skills is plus, such as PERL, TCL etc